Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 519. TPG_CONFIG0, Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x60030 15:13
TPM_SEQ0[2:0]
TPM_TPINV0
TPG_TPINV0
TPM_EDGE0
These bits select the test pattern to be monitored by the
TPG on the DS1 test input.
000
0
12
11
10
This bit, if set, inverts the received data for DS1 test sig-
nals.
This bit, if set, inverts the transmitted data for DS1 test
signals.
0
This bit, if set, selects the rising edge of XC_TCLK[0] for
use as the retiming clock edge, or else selects the falling
edge.
1
9
8
TPG_EDGE0
This bit, if set, selects the rising edge of TPG_CLK[0] for
use as the transmit clock edge, or else selects the falling
edge.
1
TPG_TPM_ESF_0
This bit selects extended superframe mode for DS1 test
signals.
0
7:6 TPG_TPM_CODE0[1:0] Do not use line coding/decoding when 00.
Use HDB3 coding/decoding when 01.
00
Use B8ZS coding/decoding when 10.
Use AMI coding/decoding when 11.
This code is common to the generator and monitor sides.
This bit is set to select a framed DS1 test pattern in the
monitor.
5
4
TPM_FRAME0
TPG_FINV0
0
0
If this bit is set, the frame bit in the twelfth frame of each
superframe is inverted in the DS1 test pattern.
3
TPG_FRAME0
TPG_SEQ0[2:0]
This bit is set to select a framed DS1 test pattern in the
generator.
0
2:0
These bits select the test pattern to be generated and
transmitted by the TPG on the DS1 test output.
000
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = alternating 01
101 = all ones
110 = unused
111 = user defined
Agere Systems Inc.
351
ETC [ ETC ]
