TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
15 Test-Pattern Generation/Detection Registers (continued)
15.2 Test-Pattern Generation/Detection Register Map
Table 532. Test-Pattern Generation/Detection Register Map
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
Address
Symbol
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Block-Level Status—RO
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x60000
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TPG_ID
RSVD
TPG_READY
TPG_VERSION[2:0]
TPG_ID[7:0]
0x60001
—
0x60003
TPM Interrupt Sources (Deltas and Events)—RO
0x60004
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TPG_ISRC_OOFD
TPG_ISRC_OOSD
TPG_ISRC_BERE
TPG_ISRC_FERE
TPG_ISRC_BPVE
TPG_ISRC_AISD
TPG_ISRC_CRCE
RSVD
TPM_OOF2D
TPM_OOS2D
TPM_BERE2
TPM_FERE2
TPM_BPEV2
TPM_AIS2D
TPM_CRCE2
TPM_OOF0D
TPM_OOS0D
TPM_BERE0
TPM_FERE0
TPM_BPEV0
TPM_AIS0D
TPM_CRCE0
0x60005
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TPM_OOS5D
TPM_OOS4D
TPM_BERE4
0x60006
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TPM_BERE5
TPM_AIS5D
0x60007
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0x60008
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0x60009
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TPM_AIS4D
0x6000A
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0x6000B
—
0x6000F
TPM Interrupt Masks—R/W and Edge Controls
0x60010
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TPG_IMSK_OOFD
TPG_IMSK_OOSD
TPG_IMSK_BERE
TPG_IMSK_FERE
TPG_IMSK_BPV
TPG_IMSK_AISD
TPM_OOF2DM
TPM_OOS2DM
TPM_BERE2M
TPM_FERE2M
TPM_BPV2M
TPM_AIS2DM
TPM_OOF0DM
TPM_OOS0DM
TPM_BERE0M
TPM_FERE0M
TPM_BPV0M
TPM_AIS0DM
0x60011
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TPM_OOS5DM
TPM_BERE5M
TPM_OOS4DM
TPM_BERE4M
0x60012
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0x60013
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0x60014
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0x60015
TPM_AIS5DM
TPM_AIS4DM
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Agere Systems Inc.
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