TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 401. FRM_PMLR8, Performance Monitor Link Register 8 (COR)
Address* Bit
Name
Function
Reset
Default
0x8LP87 15:0 FRM_FBEC[15:0] Frame Bit Error Counter.
0x0
DS1: This register contains the 16-bit count of received framing
bit errors. Framing bit errors are not counted during loss of
frame alignment. (T1.231, Section 6.1.1.2.2.)
CEPT: This register contains the 16-bit count of received frame
alignment signal errors. Optionally, bit 2 of NOTFAS frames can
be counted.
Note: A FAS with errors in two or more bit positions is only
counted once.
* See Table 393 on page 279 for values of L and P.
Table 402. FRM_PMLR9, Performance Monitor Link Register 9 (COR)
Address* Bit Name Function
Reset
Default
0x8LP88 15:0 FRM_CEC[15:0] CRC Error Counter. This register contains the 16-bit count of
received CRC errors. CRC errors are not counted during loss of
CRC multiframe alignment.
0x0
* See Table 393 on page 279 for values of L and P.
Table 403. FRM_PMLR10, Performance Monitor Link Register 10 (COR)
Address* Bit
Name
Function
Reset
Default
0x8LP89 15:0 FRM_REC[15:0] Receive E-bit Counter. This register contains the 16-bit count of
received E bit = 0 events. E bit = 0 events are not counted during
loss of CEPT CRC-4 multiframe alignment.
0x0
* See Table 393 on page 279 for values of L and P.
Table 404. FRM_PMLR11, Performance Monitor Link Register 11 (COR)
Address* Bit
Name
Function
Reset
Default
0x8LP8A 15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Counter. This register contains the 16-bit
count of received Sa6 = 00x1 events. The Sa6 code is detected
synchronously to the CRC-4 multiframe and is not counted dur-
ing loss of CRC-4 multiframe alignment. This detection is not
qualified by Sa5 = 1.
0x0000
* See Table 393 on page 279 for values of L and P.
Table 405. FRM_PMLR12, Performance Monitor Link Register 12 (COR)
Address* Bit
Name
Function
Reset
Default
0x8LP8B 15:0 FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the 16-bit
count of received Sa6 = 001x events. The Sa6 code is detected
synchronously to the CRC-4 multiframe and is not counted dur-
ing loss of CRC-4 multiframe alignment. This detection is not
qualified by Sa5 = 1.
0x0000
* See Table 393 on page 279 for values of L and P.
290
Agere Systems Inc.
ETC [ ETC ]
