Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 376. FRM_SGR6, Receive Signaling Global Register 6
Address
Bit
Name
Function
Reset
Default
Reserved. Reads 0.
0x80065
15:3
2
RSVD
0
0
FRM_R_COSDTHI Receive Signaling Change of State FIFO Depth Thresh-
old Overflow Interrupt. This interrupt status bit will be set
when the programmed threshold for the FIFO capacity has
been exceeded. This interrupt bit can be reset based on a
clear-on-read protocol, which is provisioned in the Super-
mapper global registers.
1
0
FRM_R_COSTTHI Receive Signaling Change of State FIFO Timer Thresh-
old Interrupt. This interrupt status bit will be set when the
programmed interrupt timer has expired and there are valid
entries in the FIFO to be processed. This interrupt bit can be
reset based on a clear-on-read protocol, which is provisioned
in the Supermapper global registers.
0
0
FRM_R_COSOFI Receive Signaling Change of State FIFO Overflow Inter-
rupt. This interrupt status bit will be set when the signaling
change of state FIFO overflows. The contents of the FIFO
will be lost and the programmed threshold for the FIFO
capacity has been exceeded. This interrupt bit can be reset
based on a clear-on-read protocol, which is provisioned in
the Supermapper global registers.
Table 377. FRM_SGR7, Receive Signaling Global Register 7 (R/W)
Address
Bit
Name
Function
Reset
Default
Reserved. Reads 0.
0x80066
15:3
2
RSVD
0
1
FRM_R_COSDTHM Receive Signaling Change of State FIFO Depth Thresh-
old Overflow Interrupt Mask. The corresponding interrupt
status bit will cause a processor interrupt if this bit is set to 0.
The corresponding interrupt status bit will be masked from
causing a processor interrupt if this bit is set to 1.
1
0
FRM_R_COSTTHM Receive Signaling Change of State FIFO Timer Thresh-
old Interrupt Mask. The corresponding interrupt status bit
will cause a processor interrupt if this bit is set to 0. The cor-
responding interrupt status bit will be masked from causing a
processor interrupt if this bit is set to 1.
1
1
FRM_R_COSOFM Receive Signaling Change of State FIFO Overflow Inter-
rupt Mask. The corresponding interrupt status bit will cause
a processor interrupt if this bit is set to 0. The corresponding
interrupt status bit will be masked from causing a processor
interrupt if this bit is set to 1.
Agere Systems Inc.
269
ETC [ ETC ]
