Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 365. FRM_SYSGR7, System Interface Global Register 7 (COR)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80056
15:1
0
RSVD
0x0
0
FRM_TPSB_FS_IS Transmit PSB Frame Sync Error Interrupt. A 1 indicates
a frame sync error was detected in PSB mode. The frame
sync was either detected when it should not have been
(misplaced) or was not detected when it should have been
(missing). This bit is cleared on read/write unless the condi-
tion that set it still exists after the read.
Table 366. FRM_SYSGR8, System Interface Global Register 8 (R/W)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80057
15:1
0
RSVD
0
1
FRM_PSB_FS_IM Transmit PSB Frame Sync Interrupt Mask. A 1 prevents
the FRM_TPSB_FS_IS (Table 365 on page 265) status
from causing an interrupt. A 0 allows the interrupt.
Table 367. FRM_SYSGR9, System Interface Global Register 9 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80150
15
FRM_RS_DPAR
Receive PSB Data Parity Select. This bit is only applica-
ble in the parallel system bus interface mode. Otherwise, it
should be set to 0.
0
0 = odd data parity is expected by the receive system.
1 = even data parity is expected by the receive system.
14
13
FRM_RS_SPAR
FRM_RFSCKE
Receive Signaling Parity Select. This bit applies to the
signaling information in the parallel system bus mode. It
also determines the parity for CHI ASM mode. Otherwise,
it should be set to 0.
0
0 = odd signaling parity is expected by the receive system.
1 = even signaling parity is expected by the receive system.
System Interface Receive Frame Sync Clock Edge
Select.
0
0 = receive frame sync (and data) is sampled on the falling
edge of receive clock.
1 = receive frame sync (and data) is sample on the rising
edge of receive clock.
In parallel system bus mode, this bit also determines the
clock edge used to sample data.
In CHI mode, the sample point of frame sync defines the
zero offset for the CHI.
12:0
RSVD
Reserved. Must write to 0.
0
Agere Systems Inc.
265
ETC [ ETC ]
