Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
12.6 Signaling Global Registers
Table 371. FRM_SGR1, Receive Signaling Global Register 1 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80060
15
FRM_R_TSAISHG
System AIS for Handling Groups. When set to 1, this
configuration bit forces AIS to the system interface for
those signaling bits which correspond to a handling
group, which is out of alignment. A 0 disables this fea-
ture. This feature is only applied to those links which are
enabled for byte sync mapping and handling groups
using the per-link signaling configuration registers.
0
14:10 FRM_R_LINKCNT[4:0] Receive Link Count. Indicates the number of links ser-
viced by the signaling block. This value should be set to
28 when the Supermapper is interfacing with only DS1
links; it should be set to the actual number of links active
for mixed mode applications.
28
9
RSVD
Reserved. Must write to 0.
0
000
0
8:6
5:2
1
FRM_TEST_BIT[2:0] Test Bits.
RSVD
Reserved. Must write to 0.
FRM_R_AFZFBE
Automatic Signaling Freeze on Framing Bit Errors.
Set to 1 in order to freeze signaling register updates
based on framing bit errors.
0
0
RSVD
Reserved. Must write to 0.
Table 372. FRM_SGR2, Receive Signaling Global Register 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80061
15
FRM_R_SCOSEN
Receive Signaling Change of State FIFO Enable.
When set to 1, this configuration bit enables the mainte-
nance of the signaling change of state FIFO. When set to
0, no entries will be made into the FIFO. This bit applies
to all of the links. If an individual time slot is programmed
for no signaling, then no entries will be made for that time
slot. Also, if the signaling source in the receive path is set
to host, then no entries will be made for that time slot.
0
14:10
9:0
RSVD
Reserved. Must write to 0.
0
0
FRM_R_SCOSDTH[9:0] Receive Signaling Change of State FIFO Depth
Threshold. This number can be programmed from 0 to
672. If the number of entries in the signaling change of
state FIFO exceeds the value programmed here, then
the associated interrupt status bit will be set.
Agere Systems Inc.
267
ETC [ ETC ]
