Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 356. FRM_HGR18, Receive HDLC Global Register 18 (R/W)
Address Bit Name Function
Reset
Default
0x80043 15:0 FRM_RH_IS[31:16] Receive HDLC Interrupt Summary. This bitmap shows what
channels have interrupts. This register maps channels 31—16
to bits 15:0.
0
Table 357. FRM_HGR19, Receive HDLC Global Register 19 (R/W)
Address Bit
Name
Function
Reset
Default
0x80044 15:0 FRM_RH_IS[47:32] Receive HDLC Interrupt Summary. This bitmap shows what
channels have interrupts. This register maps channels 47—32
to bits 15:0.
0
Table 358. FRM_HGR20, Receive HDLC Global Register 20 (R/W)
Address Bit
Name
Function
Reset
Default
0x80045 15:0 FRM_RH_IS[63:48] Receive HDLC Interrupt Summary. This bitmap shows what
channels have interrupts. This register maps channels 63—48
to bits 15:0.
0
12.5 System Interface Global Registers
Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W)
Address Bit
Name
Function
Reset
Default
0x80050 15:12 FRM_SYSMOD[3:0] System Interface Mode Associated Signaling Mode.
0000 = 2.048 Mbits/s CHI.
0000
0001 = 4.096 Mbits/s CHI.
0010 = 8.192 Mbits/s CHI.
0100 = 19.44 Mbits/s PSB (device 0 mode).
0101 = 19.44 Mbits/s PSB (device 1 mode).
0110 = 19.44 Mbits/s PSB (device 2 mode).
1000 = SMI.
All others: Reserved.
11
FRM_ASM
System Interface Mode Associated Signaling Mode.
0
0 = CHI is configured to carry payload data only.
In PSB mode, transmit signaling is 3-stated, and receive sig-
naling ignored.
1 = CHI is configured to carry both payload data and signaling
information. Each time slot consists of 16 bits, where
8 bits are data and the remaining 8 bits are signaling infor-
mation. CHI must be programmed for 4.096 Mbits/s or
8.192 Mbits/s modes.
In PSB mode, transmit signaling is driven and receive signal-
ing is forwarded to the signaling block.
Agere Systems Inc.
261
ETC [ ETC ]
