TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 362. FRM_SYSGR4, System Interface Global Register 4 (R/W)
Address
Bit
Name
Function
Reset
Default
CHI Time-Slot System Loopback.
0x80053
15
FRM_STSSLB
0
0 = no action.
1 = receive CHI time slot is looped back to the system. Idle
code, FRM_IDLE[7:0] (Table 361 on page 263), is
inserted in place of the looped back time slot to the
line.
CHI Time-Slot Line Loopback.
14
13
FRM_STSLLB
RSVD
0
0 = no action.
1 = transmit CHI time slot is looped back to the line. Idle
code, FRM_IDLE[7:0], is inserted in place of the
looped back time slot to the system.
Reserved. Must write to 0.
0
CHI Time-Slot Loopback Address.
Reserved. Must write to 0.
12:8 FRM_TSLBA[4:0]
00000
0
7:5
4:0
RSVD
CHI Time-Slot Loopback Link Number.
FRM_TSLBL[4:0]
00000
Table 363. FRM_SYSGR5, System Interface Global Register 5 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80054
15
FRM_TS_DPAR Transmit PSB Data Parity. This bit is only applicable in
the parallel system bus mode. Otherwise, it should be set
to zero.
0
0 = odd data parity is transmitted by the system.
1 = even data parity is transmitted by the system.
14
FRM_TS_SPAR Transmit Signaling Parity. This bit applies to the signaling
information in the parallel system bus mode. It also deter-
mines the parity for CHI ASM mode. Otherwise, it should
be set to 0.
0
0 = odd signaling parity is transmitted by the system.
1 = even signaling parity is transmitted by the system.
Reserved. Must write to 0.
13:0
RSVD
0
Table 364. FRM_SYSGR6, System Interface Global Register 6 (COR)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80055
15:0
RSVD
0x0000
264
Agere Systems Inc.
ETC [ ETC ]
