Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W) (continued)
Address Bit
Name
Function
Reset
Default
System Interface Transmit Frame Sync Clock Edge Select.
0x80050
4
FRM_TFSCKE
0
0 = transmit frame sync is sampled on the falling edge of
transmit clock.
1 = transmit frame sync is sampled on the rising edge of
transmit clock.
In PSB mode, this bit also determines the clock edge used to
drive data. The sampling point of transmit frame sync defines
the zero offset for CHI mode.
Frame Sync Polarity.
3
FRM_FSPOL
RSVD
0
0
0 = transmit and receive frame sync is active-low.
1 = transmit and receive frame sync is active-high.
Reserved. Must write to 0.
2:0
Table 360. FRM_SYSGR2, System Interface Global Register 2 (R/W)
Address Bit
Name
Function
Reset
Default
0x80051
15
FRM_HWYENA
Transmit System Interface Highway Enable.
0
0 = transmit data is forced into a high-impedance state for all
transmitted time slots. Receive system ignores receive
data and inserts the idle code in all time slots transmitted
to the line. This allows the framer to be fully configured
before transmission.
1 = transmit and receive data is enabled.
14
FRM_RSTDONE Framer Reset Status.
0
0
0 = indicates internal reset is still in process.
(Read Only)
1 = indicates internal reset is complete.
Generally, the FRM_HWYENA bit should not be set to1 until
this bit reads 1.
Reserved. Must write to 0.
13:0
RSVD
Table 361. FRM_SYSGR3, System Interface Global Register 3 (R/W)
Address Bit
Name
Function
Reset
Default
Stuffed Time-Slot Code.
CHI Time-Slot Loopback Idle Code.
0x80052 15:8
7:0
FRM_STUFF[7:0]
FRM_IDLE[7:0]
7F
7F
Agere Systems Inc.
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