TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
12 28-Channel Framer Registers (continued)
Table 350. FRM_HGR12, Transmit HDLC Global Register 12 (R/W)
Address
Bit
Name
Function
Reset
Default
0x8014B
15:0
FRM_TH_IS[31:16]
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 31—16 to bits 15:0.
0x0000
Table 351. FRM_HGR13, Transmit HDLC Global Register 13 (R/W)
Address
Bit
Name
Function
Reset
Default
0x8014C
15:0
FRM_TH_IS[47:32]
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 47—32 to bits 15:0.
0x0000
Table 352. FRM_HGR14, Transmit HDLC Global Register 14 (R/W)
Address
Bit
Name
Function
Reset
Default
0x8014D
15:0
FRM_TH_IS[63:48]
Transmit HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 63—48 to bits 15:0.
0x0000
Table 353. FRM_HGR15, Receive HDLC Global Register 15 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80040
15:10
9:0
RSVD
Reserved. Must write to 0.
0x00
FRM_HRTHRSH0[9:0] Indicates the Threshold Levels for the Rx FIFOs.
0x000
When a channel is enabled and its FIFO count incre-
ments to this value, its FRM_HRTHRSH (Table 455 on
page 314) status bit is set. FRM_HRTHRSH0 or
FRM_HRTHRSH1 is selected on a per-channel basis
with the FRM_RTHRSEL (Table 454 on page 313)
parameter.
Table 354. FRM_HGR16, Receive HDLC Global Register 16 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80041
15:10
9:0
RSVD
Reserved. Must write to 0.
0x00
FRM_HRTHRSH1[9:0] Indicates the Threshold Levels for the Rx FIFOs.
When a channel is enabled and its FIFO count incre-
ments to this value, its FRM_HRTHRSH status bit is
set. FRM_HRTHRSH0[9:0] or FRM_HRTHRSH1[9:0]
is selected on a per-channel basis with the
0x000
FRM_RTHRSEL (Table 454 on page 313) parameter.
Table 355. FRM_HGR17, Receive HDLC Global Register 17 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80042
15:0
FRM_RH_IS[15:0]
Receive HDLC Interrupt Summary. This bitmap
shows what channels have interrupts. This register
maps channels 15—0 to bits 15:0.
0
260
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