Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers (continued)
Table 337. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x80P3E
15:0
FRM_LN_IS[16:1]
Per-Link PM Summary Interrupts for Links 16 Down
to 1.
0x0000
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
Table 338. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)
Address*
Bit
Name
Function
Reset
Default
0x80P3F 15:12
11:0
RSVD
Reserved. Must write to 0.
0x0
FRM_LN_IS[28:17] Per-Link PM Summary Interrupts for Links 28 Down
0x000
to 17.
*
P = 0x0 for the receive path, and P = 0x1 for the transmit path.
12.4 HDLC Global Configuration and Status Registers
Table 339. FRM_HGR1, Transmit HDLC Global Register 1 (R/W)
Address
Bit
Name
Function
Reset
Default
Reserved. Must write to 0.
0x80140 15:10
RSVD
0x00
9:0 FRM_HTTHRSH0[9:0] HDLC Transmit FIFO Threshold 0. These bits indicate
the threshold levels for the Tx FIFOs. When a channel is
enabled and the number of bytes in its FIFO decrements
to this value, its FRM_HTTHRSH (Table 448 on
0x000
page 311) bit is set (optionally causes interrupt).
FRM_HTTHRSH0[9:0] or FRM_HTTHRSH1[9:0] is
selected on a per-channel basis with the
FRM_HTTHRSEL (Table 447 on page 310) parameter.
Table 340. FRM_HGR2, Transmit HDLC Global Register 2 (R/W)
Address
Bit
Name
Function
Reset
Default
0x80141 15:10
RSVD
Reserved. Must write to 0.
0x00
9:0 FRM_HTTHRSH1[9:0] HDLC Transmit FIFO Threshold 1. These bits indicate
the threshold levels for the Tx FIFOs. When a channel is
enabled and the number of bytes in its FIFO decrements
to this value, its FRM_HTTHRSH bit is set (optionally
causes interrupt). FRM_HTTHRSH0[9:0] or
0x000
FRM_HTTHRSH1[9:0] is selected on a per-channel basis
with the FRM_HTTHRSEL (Table 447 on page 310)
parameter.
Agere Systems Inc.
257
ETC [ ETC ]
