a-Si TFT LCD Single Chip Driver
240RGBx320 Resolution and 262K color
ILI9325
8.2.11. RGB Display Interface Control 1 (R0Ch)
R/W RS
D15 D14
D13
D12 D11 D10 D9 D8 D7 D6
D5
D4
D3 D2
D1
D0
W
1
0
ENC2 ENC1 ENC0
0
0
0
RM
0
0
DM1 DM0
0
0
RIM1 RIM0
RIM[1:0] Select the RGB interface data width.
RIM1 RIM0 RGB Interface Mode
0
0
0
1
18-bit RGB interface (1 transfer/pixel), DB[17:0]
16-bit RGB interface (1 transfer/pixel), DB[17:13] and DB[11:1]
1
1
0
1
6-bit RGB interface (3 transfers/pixel), DB[17:12]
Setting disabled
Note1: Registers are set only by the system interface.
Note2: Be sure that one pixel (3 dots) data transfer finished when interface switch.
DM[1:0] Select the display operation mode.
DM1
DM0
Display Interface
Internal system clock
RGB interface
0
0
0
1
1
1
0
1
VSYNC interface
Setting disabled
The DM[1:0] setting allows switching between internal clock operation mode and external display
interface operation mode. However, switching between the RGB interface operation mode and the
VSYNC interface operation mode is prohibited.
RM Select the interface to access the GRAM.
Set RM to “1” when writing display data by the RGB interface.
RM
Interface for RAM Access
0
System interface/VSYNC interface
1
RGB interface
Display State
Operation Mode
RAM Access (RM) Display Operation Mode (DM[1:0]
System interface
(RM = 0)
Internal clock operation
(DM[1:0] = 00)
RGB interface
Still pictures
Internal clock operation
RGB interface
(RM = 1)
Moving pictures
RGB interface (1)
(DM[1:0] = 01)
RGB interface
(DM[1:0] = 01)
VSYNC interface
(DM[1:0] = 10)
Rewrite still picture area while RGB interface
Displaying moving pictures.
System interface
(RM = 0)
System interface
(RM = 0)
Moving pictures
VSYNC interface
Note 1: Registers are set only via the system interface or SPI interface.
Note 2: Refer to the flowcharts of “RGB Input Interface” section for the mode switch.
ENC[2:0] Set the GRAM write cycle through the RGB interface
ENC[2:0]
000
GRAM Write Cycle (Frame periods)
1 Frame
2 Frames
3 Frames
4 Frames
001
010
011
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