Proprietary TranSwitch Corporation Information for use Solely by its Customers
L3M
TXC-03452B
DATA SHEET
Figure 18. STS-1 Add/Drop Bus Interface Timing
tCYC
tPWH
DCLK
(INPUT)
tH(1)
tSU(1)
DDATA(7-0)
DPAR
SPE
C1
J1
SPE
SPE
(INPUTS)
tH(2)
tSU(2)
DSPE
(INPUT)
tH(1)
tSU(1)
DC1J1
(INPUT)
C1(3)
J1
tOD(1)
tOD(3)
ADATA(7-0)
APAR
(OUTPUTS)
SPE
J1
SPE
SPE
tOD(2)
tOD(4)
ADD
(OUTPUT)
Note: The relationship between J1 and the SPE signals is shown for illustration purposes only, and will
be a function of the pointer offset. For the STS-1 format, there will be one J1 pulse which indicates
the start of the STS-1. The C1 pulse is shown dotted because the C1 pulse may be provided on
the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter
DCLK clock period
Symbol
Min
Typ
Max
Unit
tCYC
--
154.32
50
ns
%
DCLK duty cycle, tPWH/tCYC
40
60
DDATA(7-0) data/DPAR/DC1J1 set-up
tSU(1)
7.0
ns
time to DCLK↓
DDATA(7-0) data/DPAR/DC1J1 hold time
tH(1)
3.0
ns
after DCLK↓
DSPE set-up time to DCLK↓
DSPE hold time after DCLK↓
tSU(2)
tH(2)
10.0
5.0
ns
ns
ns
ADATA(7-0) data and APAR delay after
tOD(1)
3.0
30
DCLK↑
ADD indicator delayed after DCLK↑
tOD(2)
tOD(3)
3.0
12
25
25
ns
ns
ADATA(7-0) data and APAR tri-state after
DCLK↑
ADD indicator high after DCLK↑
tOD(4)
12
25
ns
TXC-03452B-MB
Ed. 6, April 2001
- 38 of 96 -
ETC [ ETC ]
