Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 to 0: IRQ4 to IRQ0 interrupt request flags (IRRI4 to IRRI0)
Bit n
IRRIn
Description
0
Clearing conditions:
(initial value)
When IRRIn = 1, it is cleared by writing 0
1
Setting conditions:
When pin IRQn is designated for interrupt input and the designated
signal edge is input
(n = 4 to 0)
5. Interrupt request register 2 (IRR2)
Bit
7
6
5
—
4
3
2
1
0
IRRDT IRRAD
IRRTG IRRTFH IRRTFL IRRTC IRREC
Initial value
Read/Write
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
R/(W)
R/(W)
R/(W)
R/W
R/(W)
R/(W)
R/(W)
R/(W)
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
(initial value)
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2
74
ETC [ ETC ]
