Bit 1: Timer C interrupt request flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing conditions:
(initial value)
When IRRTC= 1, it is cleared by writing 0
1
Setting conditions:
When the timer C counter value overflows (from H'FF to H'00) or underflows
(from H'00 to H'FF)
Bit 0: Asynchronous event counter interrupt request flag (IRREC)
Bit 0
IRREC
Description
0
Clearing conditions:
(initial value)
When IRREC = 1, it is cleared by writing 0
1
Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
6. Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Initial value
Read/Write
0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)
Note:
*
All bits can only be written with 0, for flag clearing.
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
76
ETC [ ETC ]
