Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0)
Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests.
Bit n
IENn
Description
0
1
Disables interrupt requests from pin IRQn
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 to 0)
3. Interrupt enable register 2 (IENR2)
Bit
7
IENDT
0
6
IENAD
0
5
—
4
3
2
1
0
IENTG IENTFH IENTFL IENTC IENEC
Initial value
Read/Write
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
1
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
(initial value)
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
1
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
(initial value)
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
71
ETC [ ETC ]
