Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
1
Disables asynchronous event counter interrupt requests
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in
section 10.4.2.
4. Interrupt request register 1 (IRR1)
Bit
7
IRRTA
0
6
IRRS1
0
5
—
1
4
IRRI4
0
3
IRRI3
0
2
IRRI2
0
1
IRRI1
0
0
IRRI0
0
Initial value
Read/Write
*
*
*
*
*
*
*
R/(W)
R/(W)
R/(W)
—
R/(W)
R/(W)
R/(W)
R/(W)
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
(initial value)
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
Description
0
Clearing conditions:
(initial value)
When IRRS1 = 1, it is cleared by writing 0
1
Setting conditions:
When SCI1 completes transfer
73
ETC [ ETC ]
