Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
1
Disables timer G interrupt requests
Enables timer G interrupt requests
(initial value)
(initial value)
(initial value)
(initial value)
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
1
Disables timer FH interrupt requests
Enables timer FH interrupt requests
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
1
Disables timer FL interrupt requests
Enables timer FL interrupt requests
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
1
Disables timer C interrupt requests
Enables timer C interrupt requests
72
ETC [ ETC ]
