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EP20K200RC208-1 参数 Datasheet PDF下载

EP20K200RC208-1图片预览
型号: EP20K200RC208-1
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列
文件页数/大小: 114 页 / 1501 K
品牌: ETC [ ETC ]
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APEX 20K Programmable Logic Device Family Data Sheet  
Figure 28 shows how a column IOE connects to the interconnect.  
Figure 28. Column IOE Connection to the Interconnect  
Each IOE can drive column interconnect. In APEX 20KE devices,  
IOEs can also drive FastRow interconnect. Each IOE data  
and OE signal is driven by local interconnect.  
IOE  
IOE  
An LE or ESB can drive a  
pin through a local  
interconnect for faster  
clock-to-output times.  
LAB  
Any LE or ESB can drive  
a column pin through a  
row, column, and MegaLAB  
interconnect.  
Column Interconnect  
MegaLAB Interconnect  
Row Interconnect  
Dedicated Fast I/O Pins  
APEX 20KE devices incorporate an enhancement to support bidirectional  
pins with high internal fanout such as PCI control signals. These pins are  
called Dedicated Fast I/ O pins (FAST1, FAST2, FAST3, and FAST4) and  
replace dedicated inputs. These pins can be used for fast clock, clear, or  
high fanout logic signal distribution. They also can drive out. The  
Dedicated Fast I/ O pin data output and tri-state control are driven by  
local interconnect from the adjacent MegaLAB for high speed.  
Altera Corporation  
43  
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