APEX 20K Programmable Logic Device Family Data Sheet
Figure 26. APEX 20KE Bidirectional I/O Registers
Notes (1), (2)
Row, Column, FastRow,
4 Dedicated
or Local Interconnect Clock Inputs
Peripheral Control
Bus
4 Dedicated
Inputs
OE Register
D
Q
ENA
VCC
CLRN
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
OE[7..0]
VCCIO
Input Pin to
Optional
Core Delay (1)
PCI Clamp
Input Pin to
Core Delay (1)
12
4
VCC
Output Register
Delay
Output Register
Core to Output
Register Delay
t
CO
Q
D
Open-Drain
Output
Input Pin to Input
Register Delay
ENA
CLK[1..0]
CLRN/
PRN
Slew-Rate
Control
CLK[3..0]
ENA[5..0]
VCC
Clock Enable
Delay (1)
VCC
CLRn[1..0]
Input Pin to
Core Delay (1)
Chip-Wide
Reset
Input Register
D
Q
VCC
ENA
CLRN
VCC
Chip-Wide
Reset
Notes:
(1) This programmable delay has four settings: off and three levels of delay.
(2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
Altera Corporation
41
ETC [ ETC ]
