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RTL8100CL-LF 参数 Datasheet PDF下载

RTL8100CL-LF图片预览
型号: RTL8100CL-LF
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
6.5. PCI Power Management Functions  
The RTL8100C(L) complies with ACPI (Rev 1.1), PCI Power Management (Rev 1.1), and the Device  
Class Power Management Reference Specification (V1.0a), such as to support an Operating  
System-Directed Power Management (OSPM) environment. To support this, the RTL8100C(L) provides  
the following capabilities:  
The RTL8100C(L) can monitor the network for a Wakeup Frame (AMD Magic Packet, LinkChg,  
Microsoft® wake-up frame), and notify the system via PME# should such a packet or event arrive.  
Then the system can be restored to a working state to process incoming jobs.  
The RTL8100C(L) can be isolated from the PCI bus automatically via the auxiliary power circuit when  
the PCI bus is in B3 state, i.e. the power on the PCI bus is removed. The RTL8100C(L) can be disabled  
when needed by pulling the isolate pin low to 0V.  
6.5.1. Power Down Mode  
When the RTL8100C(L) is in power down mode (D1 ~ D3):  
The Rx state machine is stopped and the RTL8100C(L) monitors the network for wakeup events. The  
RTL8100C(L) will not reflect the status of any incoming packets in the ISR register and will not receive  
any packets into the Rx FIFO.  
The FIFO status and the packets that are already in the Rx FIFO before entering power down mode are  
held by the RTL8100C(L) during power down mode.  
Transmission is stopped. PCI bus master mode is stopped. The Tx FIFO buffer is held.  
After restoration to a D0 state, PCI bus master mode transfers data to the Tx FIFO that was not moved  
into the Tx FIFO before the last break. Apacket that was not transmitted completely before power down  
mode is transmitted again.  
D3cold_support_PME bit (bit15, PMC register) & Aux_I_b2:0 (bit8:6, PMC register) in PCI  
configuration space  
If 9346 D3cold_support_PME bit (bit15, PMC) = 1, the above 4 bits depend on the existence of  
Aux power.  
If 9346 D3cold_support_PME bit (bit15, PMC) = 0, the above 4 bits are all 0’s.  
Examples:  
1. 9346 D3c_support_PME = 1  
If Aux. power exists, then PMC in PCI config space is the same as 9346 PMC,  
i.e. if 9346 PMC = C2 F7, then PCI PMC = C2 F7.  
Aux. power is absent, then PMC in PCI config space is the same as 9346 PMC except the above  
4 bits are all 0’s. I.e. if 9346 PMC = C2 F7, then PCI PMC = 02 76.  
Note: In this case, if wakeup support is desired when the main power is off, it is suggested that the  
EEPROM PMC be set to: C2 F7 (Realtek default value). It is not recommended to set the D0_support_PME  
bit to 1.  
Single-Chip Fast Ethernet Controller  
45  
Track ID: JATR-1076-21 Rev. 1.06  
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