RTL8100C & RTL8100CL
Datasheet
7. Functional Description
7.1. Transmit Operation
The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main
memory. When the entire packet has been transferred to the Tx buffer, the RTL8100C(L) is instructed to
move the data from the Tx buffer to the internal transmit FIFO in PCI bus master mode. When the transmit
FIFO contains a complete packet or is filled to the programmed threshold level, the RTL8100C(L) begins
packet transmission.
7.2. Receive Operation
The incoming packet is placed in the RTL8100C(L)’s Rx FIFO. Concurrently, the RTL8100C(L) performs
address filtering of multicast packets according to the hash algorithms. When the amount of data in the Rx
FIFO reaches the level defined in the Receive Configuration Register, the RTL8100C(L) requests the PCI
bus to begin transferring the data to the Rx buffer in PCI bus master mode.
7.3. Wander Compensation
The 8100C(L) is ANSI TP-PMD compliant and supports Input Wander and Base Line Wander (BLW)
compensation in 100Base-TX mode. The 8100C(L) does not require external attenuation circuitry at its
receive inputs, RD+/-. It accepts TP-PMD compliant waveforms directly, requiring only 100Ω termination
and a 1:1 transformer.
BLW is the change in the average DC content, over time, of an AC coupled digital transmission over a
given transmission medium and is a result of the interaction between the low frequency components of a
transmitted bit stream and the frequency response of the AC coupling component(s) within the transmission
system. If the low frequency content of the digital bit stream goes below the low frequency pole of the AC
coupling transformers, then the droop characteristics of the transformers will dominate, resulting in
potentially serious BLW. If BLW is not compensated, packet loss can occur.
7.4. Signal Detect
The 8100C(L) supports signal detect in 100Base-TX mode. The reception of normal 10Base-T link pulses
and fast link pulses (defined by IEEE 802.3u Auto-negotiation) by the 100Base-TX receiver do not cause
the 8100C(L) to assert signal detect.
The signal detect function of the 8100C(L) is incorporated to meet the specifications mandated by the ANSI
FDDI TP-PMD standard as well as the IEEE 802.3 100Base-TX standard for both voltage thresholds and
timing parameters.
Single-Chip Fast Ethernet Controller
49
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
