RTL8100C & RTL8100CL
Datasheet
**16-bit CRC: (Long Wakeup Frame mode, the mask bytes cover from offset 0 to 127)
Long Wakeup Frame: The RTL8100C(L) also supports 3 long Wakeup Frames. If the range of mask bytes
of the sample Wakeup Frame, passed down by the OS to the driver, exceeds the range from offset 12 to 75,
the related registers of wakeup frame 2 and 3 can be merged to support one long wakeup frame by setting
the LongWF (bit0, CONFIG4). Thus, the range of effective mask bytes extends from offset 0 to 127. The
low byte and high byte of the calculated 16-bit CRC should be put into register CRC2 and LSBCRC2
respectively. The mask bytes (16 bytes) should be stored in register Wakeup2 and Wakeup3. The CRC3
and LSBCRC3 have no meaning in this case and should be reset to 0. Long Wakeup Frame pairs are frames
4 and 5, and frames 6 and 7. The CRC5, CRC7, LSBCRC5, and LSBCRC7 have no meaning in this case
and should be set to 0 if the RTL8100C(L) is to support long Wakeup Frames. The RTL8100C(L) supports
2 normal wakeup frames and 3 long wakeup frames.
***Last Masked Byte:
The last byte of the masked bytes of the received Wakeup Frame packet within offset 12 to 75 (in 8-bit CRC
mode) should match the last byte of the masked bytes of the sample Wakeup Frame provided by the local
machine’s OS.
PME# Signal
The PME# signal is asserted only when the following conditions are met:
• The PMEn bit (bit0, CONFIG1) is set to 1.
• The PME_En bit (bit8, PMCSR) in PCI Configuration Space is set to 1.
• The RTL8100C(L) may assert PME# in current power state, or when the RTL8100C(L) is in isolation
state. Refer to 6.1 PCI Configuration Space Table, page 38, PME_Support (bit15-11) of the PMC
register.
• A Magic Packet, LinkChg, or Wakeup Frame event has occurred.
* Writing a 1 to the PME_Status (bit15) of PMCSR register in the PCI Configuration Space will clear this
bit and cause the RTL8100C(L) to stop asserting a PME# (if enabled).
When the RTL8100C(L) is in power down mode, e.g. D1-D3, the IO, and MEM are all disabled. After
RST# is asserted, the power state must be changed to D0 if the original power state was D3cold. There is no
hardware enforced delays in the RTL8100C(L)’s power state. When in ACPI mode, the RTL8100C(L)
does not support PME from D0 owing to the PMC register setting (this setting comes from EEPROM).
Single-Chip Fast Ethernet Controller
47
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
