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RTL8100CL-LF 参数 Datasheet PDF下载

RTL8100CL-LF图片预览
型号: RTL8100CL-LF
PDF下载: 下载PDF文件 查看货源
内容描述: 电源管理单芯片快速以太网控制器 [SINGLE-CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT]
分类和应用: 外围集成电路控制器LTE局域网以太网以太网:16GBASE-T
文件页数/大小: 73 页 / 652 K
品牌: ETC [ ETC ]
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RTL8100C & RTL8100CL  
Datasheet  
LWAKE Signal  
The RTL8100C(L) also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the  
motherboard to execute the wake-up process whenever the RTL8100C(L) receives a wakeup event, such as  
a Magic Packet.  
The LWAKE signal is asserted according to the following setting:  
LWPME bit (bit4, CONFIG4)  
0: LWAKE is asserted whenever a wakeup event occurs  
1: LWAKE can only be asserted when PMEB is asserted and ISOLATEB is low  
Bit1 of DELAY byte (offset 1Fh, EEPROM)  
0: LWAKE signal is disabled  
1: LWAKE signal is enabled  
6.6. VPD (Vital Product Data)  
Bit 31 of the VPD is used to issue VPD read/write commands and is also a flag used to indicate whether the  
transfer of data between the VPD data register and the 93C46 has completed or not.  
1.  
2.  
Write VPD register (write data to the 93C46)  
Write the flag bit to 1 at the same time the VPD address is written. When the flag bit is set to 0 by  
the RTL8100C(L), the VPD data (all 4 bytes) has been transferred from the VPD data register to the  
93C46.  
Read VPD register (read data from the 93C46)  
Write the flag bit to a zero at the same time the VPD address is written. When the flag bit is set to  
one by the RTL8100C(L), the VPD data (all 4 bytes) has been transferred from the 93C46 to the  
VPD data register.  
Single-Chip Fast Ethernet Controller  
48  
Track ID: JATR-1076-21 Rev. 1.06  
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