RTL8100C & RTL8100CL
Datasheet
6.4. Default Values after Power-on (RSTB Asserted)
Table 45. Default Values after Power-On (RSTB Asserted)
No.
00h
01h
02h
03h
04h
Name
VID
Type
R
R
R
R
R
W
R
W
R
R
Bit7
Bit6
1
0
0
0
0
Bit5
Bit4
0
1
1
0
0
-
0
Bit3
1
0
1
0
0
-
0
Bit2
Bit1
Bit0
1
0
0
1
0
-
0
-
0
0
1
0
1
0
0
-
0
-
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
DID
Command
PERRSP
BMEN MEMEN IOEN
05h
0
-
0
0
0
-
0
0
-
0
-
0
1
-
0
-
NewCap
0
-
0
SERREN
06h
07h
Status
0
0
DPD
0
0
STABT
0
W
R
DPERR SSERR RMABT RTABT
08h
Revision
ID
0
0
0
0
0
0
09h
0Ah
0Bh
0Ch
0Dh
PIFR
SCR
BCR
CLS
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
LTR
0
0
0
0
0
0
0
0
W
LTR7
LTR6
LTR5
LTR4
LTR3
LTP2
LTR1
LTR0
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
HTR
BIST
IOAR
R
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
MEMAR
17h
18h-2Bh
2Ch
2Dh
2Eh
2Fh
RESERVED (ALL 0)
SVID
SMID
R
R
R
R
-
1
0
0
1
-
1
0
0
0
-
1
0
0
1
1
0
1
0
-
1
0
0
0
-
0
0
0
0
-
0
1
1
1
-
1
1
0
0
30h-33h Reserved
-
-
34h
35h-3Bh
3Ch
3Dh
3Eh
Cap-Ptr
R
Ptr7
Ptr6
Ptr5
Ptr4
Ptr3
Ptr2
Ptr1
Ptr0
RESERVED (ALL 0)
ILR
IPR
MNGNT
MXLAT
-
R/W
R
R
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
3Fh
40h-FFh
R
RESERVED (ALL 0)
Single-Chip Fast Ethernet Controller
44
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
