RTL8100C & RTL8100CL
Datasheet
Table 41. PCI Configuration Space Functions
Description
Reserved.
Bit
15-10
9
Symbol
-
FBTBEN
Fast Back-To-Back Enable.
Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The RTL8100C(L) will not generate
Fast Back-to-back cycles.
When Config3<FbtBEn>=1, this read/write bit controls whether or not a master can do fast
back-to-back transactions to different devices. Initialization software will set the bit if all targets are
fast back-to-back capable.
1: The master is allowed to generate fast back-to-back transaction to different agents
0: Fast back-to-back transactions are only allowed to the same agent
This bit’s state after RST# is 0.
8
7
6
SERREN
ADSTEP
PERRSP
System Error Enable.
1: The RTL8100C(L) asserts the SERRB pin when it detects a parity error on the address phase
(AD<31:0> and CBEB<3:0>)
Address/Data Stepping.
Read as 0. Write operation has no effect.
The RTL8100C(L) never performs address/data stepping.
Parity Error Response.
1: The RTL8100C(L) will assert the PERRB pin on detection of a data parity error when acting as
the target, and will sample the PERRB pin as the master
0: Any detected parity error is ignored and the RTL8100C(L) continues normal operation
Parity checking is disabled after hardware reset (RSTB).
5
4
3
VGASNOOP VGA palette SNOOP.
Read as 0. Write operation has no effect.
MWIEN
Memory Write and Invalidate cycle Enable.
Read as 0. Write operation has no effect.
Special Cycle Enable.
SCYCEN
Read as 0. Write operation has no effect.
The RTL8100C(L) ignores all special cycle operations.
Bus Master Enable.
2
BMEN
1: The RTL8100C(L) is capable of acting as a bus master
0: The RTL8100C(L) is prohibited from acting as a PCI bus master
Normally this bit is set by the system BIOS.
Memory Space Access.
1: The RTL8100C(L) responds to memory space accesses
0: The RTL8100C(L) ignores memory space accesses
I/O Space Access.
1
0
MEMEN
IOEN
1: The RTL8100C(L) responds to IO space accesses
0: The RTL8100C(L) ignores I/O space accesses
Single-Chip Fast Ethernet Controller
40
Track ID: JATR-1076-21 Rev. 1.06
ETC [ ETC ]
