The internal VCO of the L64777 can generate OCLK, or it can use the
OCLK input. The L64777 selects OCLK based on the selected PLL mode.
OCLK drives the Nyquist filter and generates the symbol-processing clock
inside the chip after the input circular buffer. The beginning of a sync
frame at the I and Q output is indicated by the FSTARTOUT signal.
FSTARTOUT lets the L64777 watch for gap insertion in the RS code at
the FIFO read side. As long as the read pointers are halted to generate
gaps, FSTARTOUT remains HIGH for the number of RS check words plus
one cycle. For example, FSTARTOUT is one symbol clock cycle long if
no gap is inserted; it is 17 symbol clock cycles long if a gap for 16 RS
check words is inserted.
The signal FIRSTOUT indicates the head of a sequence after reset with
the SSTARTIN signal. The negative slope of the SSTARTIN input pin
controls sequence reset.
Note: DVALIDIN must be active for at least one ICLK cycle when
SSTARTIN is HIGH and when SSTARTIN is LOW.
2.3.3 Control Interface
An external CPU uses the L64777 serial control interface to control and
setup the programmable parameters of the chip. This interface is a slave-
type only, connected to the same serial bus as LSI Logic L64724.
The chip has five hardwired MSBs and takes two LSBs directly from the
input pins SB_BASE[1:0].
Bit 6, MSB
1
Bit 5
1
Bit 4
0
Bit 3
1
Bit 2
0
Bit 1
Bit 0, LSB
SB_BASE.1
SB_BASE.0
The addressing scheme in the L64777 complies with that of the
LSI Logic L64724, but due to its small, seven-bit internal address space,
the L64777 supports only group 0 and group 2 registers. It ignores all
others. Bits [2:0] within the first data byte transmitted to the device
specify the group.
2-8
Modulator Architecture
ETC [ ETC ]
