Figure 2.6 FIFO Clock Conversion
INSYNC
FIFO
SCRAMBLER
Sync Word
Block Length
Serial/Parallel
Pointer
Collision
Alarm
Sync Word
FSTARTIN
Sync
Sync
Detector
SSTARTIN
Circular
Buffer
Sync
Insert Insert
Word Flag
Error
Err.Flg.
8
Scrambler
ERRORIN
DIN[7:0]*
8
Data
128 Words
Ser/Par
Convert
ICLK domain
OCLK domain
* Note that DIN[7:0] is valid data, which is the result of D[7:0] and DVALIDIN HIGH
The L64777 synchronizes the input in the ICLK domain and transfers it
to the OCLK domain with a reserved bit in the circular buffer. It uses a
second bit to transfer the incoming error flag for further insertion into the
most significant bit (MSB) of the second byte of a sync frame, according
to the MPEG-2 standard.
The L64777 also synchronizes the SSTARTIN pin through the circular
buffer, allowing it to lock the beginning of any long-term sequence to the
SYNC_BYTE location of the next sync block. If this pin is not activated
after a reset, all generated sequences run free.
When using the L64777 with the L64724, select Parallel mode, which is
supported with external synchronization pulses. Use the SPI of L64724
in Mode 2 (204 cycle frames with DVALIDIN LOW during the check
bytes). A TEI bit set in the transport stream indicates frames with errors.
A single-line transmission connection to the serial input of the L64777
device generally requires synchronizing on the SYNC_BYTE within the
2-12
Modulator Architecture
ETC [ ETC ]
