2
Group 0 is the address pointer register (APR); the I C-Compatible Serial
Control Interface loads the address byte into APR0 (see Appendix A,
"Programming the L64777 in Serial Host Interface Mode"), for
programming details. Reading or writing from Group 2 causes a data
transfer with the device address specified by APR0:
•
If APR0 is set to zero, the Serial Control Interface expects a write
access with 196 data bytes to load the filter coefficients; it does not
apply an autoincrement to APR0.
•
If APR0 is not at zero, the Serial Control Interface expects only a
single data byte and applies an autoincrement to the APR0.
The detailed timing of the serial bus is given in Appendix A. The serial
bus runs at a maximum 400 kHz clock rate. The serial control interface
can transfer reads and writes in single-byte or burst mode. It must access
the status registers 12 and 13 with single-byte reads.
The division factor for converting OCLK down to the symbol clock is
always four. Input synchronization works at the ICLK rate, either on a bit
or byte clock. Energy dispersal (scrambling), Reed-Solomon encoding,
convolutional interleaving, byte to m-tuple conversion, differential
encoding, and QAM mapping operate at the symbol clock rate (OCLK/4).
The final Nyquist filter works on the OCLK rate.
Incoming bits are provided with an input clock (ICLK) and a validation
signal (DVALIDIN), which indicates the rising edges of ICLK that are
carrying valid data. These inputs feed into a 128-word circular FIFO
buffer. The output carries a continuous data stream if the PLL is properly
locked.
Figure 2.5 Required Relation of ICLK and DIN/DVALIDIN
DIN
Invalid Data
Valid Data
Valid Data
Invalid Data
DVALIDIN
ICLK
Input Waveforms
I/O
2-9
ETC [ ETC ]
