The QAM mapping supports 16, 32, 64, 128, and 256 QAM. The input
to the device is an MPEG-2 compliant transport stream; its output
consists of baseband QAM signals in I and Q.
2.2 PLL Modes
Connecting the L64777 to a satellite receiver and the LSI Logic satellite
decoder chip set requires the PLL circuits to lock the input and output
clocks. Two modes can achieve this:
•
•
Mode 1 uses the phase/frequency detector and the dividers of
L64777 to accept an external VCO.
Mode 2 connects the PCLK output of L64724 or L64734 to the
L64777 PCLK clock input, and connects the byte clock output to the
ICLK input of the L64777. This is also called the Numerically
Controlled Oscillator (NCO) mode of operation. This mode is
dedicated to the connection of the L64724 (see Appendix B, PLL
Divider Settings and L64724/34 Connection).
Set the PLL_MODE[1:0] pins to the values shown on page 5-6. Do not
change it during operation.
2.2.1 PLL Mode 1
Figure 2.3 shows the phase and frequency detection for an external
voltage-controlled oscillator (VCO) loop. Choose between frequency and
phase detection through the microprocessor interface.
2-4
Modulator Architecture
ETC [ ETC ]
