Synchronizing the QAM modulator with an input pulse at SSTARTIN sets
the byte and block boundaries with this external pulse. The transport
interface can reinsert the programmed sync byte at the location defined
by the external pulse.
In both the internal and external modes, the transport interface can
program the block length and the value of the sync byte. The block length
must be less than 256 bytes.
After the L64777 achieves synchronization, it either takes the sync byte
from the FIFO, or it inserts the sync byte into the modulated stream
according to the programmed sync byte. Only the latter action eliminates
any error in the input sync byte, as long as the modulator remains
synchronized (see Section 2.6.3, “Energy Dispersal (Scrambler) Unit” for
more information).
Given a bit stream consisting of a sequence of TS packets, the sync
stage searches for the preprogrammed sync byte (0x47). Upon meeting
the sync acquisition criteria, the sync stage issues the control strobes for
the downstream modules. In addition to synchronizing the L64777 to
SYNC_BYTEs contained in the input stream, the L64777 can be forced
into synchronization by external sync pulses; the modulator can be made
to reinsert the programmed SYNC_BYTE at the sync pulse position.
The transport interface can either pass on a transport error indicator
(TEI) unchanged from the input transport stream, or it can force the TEI
to indicate an error with the ERRORIN signal. The L64777 observes the
forced signal during the sync byte input and ignores it for the rest of the
input packet.
The L64777 input stage can operate either in Parallel or Serial mode.
The device receives parallel input for connection to transport layer
multiplexers at low frequency but with 11 input lines (CLK, 8 lines data,
FSTARTIN, and DVALIDIN, if required). The L64777 can mark the MPEG
frame SYNC_BYTE with a pulse on FSTARTIN to identify the beginning
of a frame. Together with FSTARTIN, the L64777 can insert sync bytes
and error-correction information into the 204 byte frames.
Figure 2.6 shows the FIFO clock conversion from the ICLK domain to the
OCLK domain.
Input Synchronization
2-11
ETC [ ETC ]
