Chapter 2
Modulator Architecture
This chapter briefly introduces the standard modulator chain and the
architecture the device uses to implement the chain. This chapter
consists of the following sections:
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Section 2.1, “Introduction,” page 2-2
Section 2.2, “PLL Modes,” page 2-4
Section 2.3, “I/O,” page 2-6
Section 2.4, “Input Synchronization,” page 2-10
Section 2.5, “FIFO Clock Conversion,” page 2-16
Section 2.6, “Sync/EF Reinsertion Unit,” page 2-17
Section 2.7, “Reed-Solomon Encoder,” page 2-20
Section 2.8, “Convolutional Interleaver,” page 2-23
Section 2.9, “Bytes to M-tuples Converter,” page 2-24
Section 2.10, “Differential Encoder and QAM Mapping,” page 2-26
Section 2.11, “Square Root Nyquist Filter,” page 2-27
Section 2.12, “Global Control and PLL Module,” page 2-34
Section 2.13, “Interpolator,” page 2-39
Section 2.14, “Serial Microprocessor Interface,” page 2-40
Section 2.15, “Test Unit,” page 2-41
L64777 DVB QAM Modulator Technical Manual
2-1
ETC [ ETC ]
