R
XC5200 Series Field Programmable Gate Arrays
CCLK
INIT
1
T
IC
T
3
CD
2
T
DC
BYTE
0
BYTE
1
BYTE
2
BYTE
3
D0-D7
Serial Data Out
(DOUT)
FPGA Filled
Internal INIT
RDY/BUSY
CS1
X5087
Description
Symbol
1 TIC
Min
5
Max
Units
µs
INIT (High) Setup time required
DIN Setup time required
DIN hold time required
CCLK High time
2
3
TDC
TCD
30
0
ns
ns
7
CCLK
T
30
30
ns
CCH
CCLK Low time
T
ns
CCL
CCLK frequency
F
10
MHz
CC
Note: If not driven by the preceding DOUT, CS1 must remain high until the device is fully configured.
Figure 38: Express Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
7-123
ETC [ ETC ]
