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XC5202-5VQ100I 参数 Datasheet PDF下载

XC5202-5VQ100I图片预览
型号: XC5202-5VQ100I
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 73 页 / 583 K
品牌: ETC [ ETC ]
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R
XC5200 Series Field Programmable Gate Arrays  
Table 13. Pin Functions During Configuration  
CONFIGURATION MODE: <M2:M1:M0>  
USER  
OPERATION  
SLAVE  
<1:1:1>  
MASTER-SER SYN.PERIPH ASYN.PERIPH MASTER-HIGH MASTER-LOW  
EXPRESS  
<0:1:0>  
<0:0:0>  
<0:1:1>  
<1:0:1>  
<1:1:0>  
<1:0:0>  
A16  
A17  
TDI  
A16  
A17  
TDI  
GCK1-I/O  
I/O  
TDI-I/O  
TCK-I/O  
TMS-I/O  
I/O  
TDI  
TCK  
TMS  
TDI  
TCK  
TMS  
TDI  
TCK  
TMS  
TDI  
TCK  
TMS  
TDI  
TCK  
TMS  
TCK  
TMS  
TCK  
TMS  
M1 (HIGH) (I)  
M0 (HIGH) (I)  
M2 (HIGH) (I)  
M1 (LOW) (I)  
M0 (LOW) (I)  
M2 (LOW) (I)  
M1 (HIGH) (I)  
M0 (HIGH) (I)  
M2 (LOW) (I)  
M1 (LOW) (I)  
M0 (HIGH) (I)  
M2 (HIGH) (I)  
M1 (HIGH) (I)  
M0 (LOW) (I)  
M2 (HIGH) (I)  
M1 (LOW) (I)  
M0 (LOW) (I)  
M2 (HIGH) (I)  
M1 (HIGH) (I)  
M0 (LOW) (I)  
M2 (LOW) (I)  
I/O  
I/O  
I/O  
GCK2-I/O  
I/O  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
HDC (HIGH)  
LDC (LOW)  
INIT-ERROR  
I/O  
I/O  
I/O  
DONE  
DONE  
DONE  
DONE  
DONE  
DONE  
DONE  
DONE  
PROGRAM  
I/O  
PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I) PROGRAM (I)  
DATA 7 (I)  
DATA 7 (I)  
DATA 7 (I)  
DATA 7 (I)  
DATA 7 (I)  
GCK3-I/O  
I/O  
DATA 6 (I)  
DATA 5 (I)  
DATA 6 (I)  
DATA 5 (I)  
CSO (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 6 (I)  
DATA 5 (I)  
DATA 6 (I)  
DATA 5 (I)  
I/O  
I/O  
DATA 4 (I)  
DATA 3 (I)  
DATA 4 (I)  
DATA 3 (I)  
RS (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 4 (I)  
DATA 3 (I)  
DATA 4 (I)  
DATA 3 (I)  
I/O  
I/O  
I/O  
DATA 2 (I)  
DATA 1 (I)  
RDY/BUSY  
DATA 0 (I)  
DOUT  
DATA 2 (I)  
DATA 1 (I)  
RDY/BUSY  
DATA 0 (I)  
DOUT  
DATA 2 (I)  
DATA 1 (I)  
RCLK  
DATA 0 (I)  
DOUT  
CCLK (O)  
TDO  
A0  
DATA 2 (I)  
DATA 1 (I)  
RCLK  
DATA 0 (I)  
DOUT  
CCLK (O)  
TDO  
A0  
DATA 2 (I)  
DATA 1 (I)  
I/O  
I/O  
I/O  
DIN (I)  
DOUT  
CCLK (I)  
TDO  
DIN (I)  
DOUT  
DATA 0 (I)  
DOUT  
I/O  
I/O  
CCLK (O)  
TDO  
CCLK (I)  
TDO  
CCLK (O)  
TDO  
CCLK (I)  
TDO  
CCLK (I)  
TDO-I/O  
I/O  
WS (I)  
A1  
A1  
GCK4-I/O  
I/O  
CS1 (I)  
A2  
A2  
CS1 (I)  
A3  
A3  
I/O  
A4  
A4  
I/O  
A5  
A5  
I/O  
A6  
A6  
I/O  
A7  
A7  
I/O  
A8  
A8  
I/O  
A9  
A9  
I/O  
A10  
A10  
I/O  
A11  
A11  
I/O  
A12  
A12  
I/O  
A13  
A13  
I/O  
A14  
A14  
I/O  
A15  
A15  
I/O  
ALL OTHERS  
Notes: 1. A shaded table cell represents a 20-kto 100-kpull-up resistor before and during configuration.  
2. (I) represents an input (O) represents an output.  
3. INIT is an open-drain output during configuration.  
7-124  
November 5, 1998 (Version 5.2)  
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