R
XC5200 Series Field Programmable Gate Arrays
Write to LCA
Read Status
RS, CS0
WS/CS0
RS, CS1
WS, CS1
1
T
CA
3
T
4
7
CD
2
T
DC
READY
BUSY
D7
D0-D7
CCLK
4
T
WTRB
6
T
BUSY
RDY/BUSY
DOUT
Previous Byte D6
D7
D0
D1
D2
X6097
Description
Symbol
Min
Max
Units
Effective Write time
1
T
100
ns
CA
(CSO, WS=Low; RS, CS1=High
Write
DIN setup time
DIN hold time
2
3
4
T
T
60
0
ns
ns
ns
DC
CD
7
RDY/BUSY delay after end of
Write or Read
T
60
60
9
WTRB
RDY/BUSY active after beginning
of Read
7
6
ns
RDY
RDY/BUSY Low output (Note 4)
T
2
CCLK
BUSY
periods
Notes: 1. Configuration must be delayed until INIT pins of all daisy-chained FPGAs are high.
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byte processing
and the phase of internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but write
may not be terminated until RDY/BUSY has been High for one CCLK period.
Figure 36: Asynchronous Peripheral Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
7-121
ETC [ ETC ]
