R
XC5200 Series Field Programmable Gate Arrays
.
A0-A17
(output)
Address for Byte n
Address for Byte n + 1
1
T
RAC
D0-D7
Byte
3
T
2
T
RCD
DRC
RCLK
(output)
7 CCLKs
CCLK
CCLK
(output)
DOUT
(output)
D6
D7
Byte n - 1
X6078
Description
Delay to Address valid
Data setup time
Symbol
TRAC
Min
Max
200
Units
1
2
3
0
60
0
ns
ns
ns
CCLK
TDRC
Data hold time
TRCD
7
Note: 1. At power-up, VCC must rise from 2.0 V to VCC min in less then 25 ms, otherwise delay configuration by pulling PROGRAM
Low until VCC is Valid.
2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
Figure 32: Master Parallel Mode Programming Switching Characteristics
November 5, 1998 (Version 5.2)
7-117
ETC [ ETC ]
