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ASI4UC-G1-SR 参数 Datasheet PDF下载

ASI4UC-G1-SR图片预览
型号: ASI4UC-G1-SR
PDF下载: 下载PDF文件 查看货源
内容描述: 通用执行器,传感器接口IC [Universal Actuator-Sensor Interface IC]
分类和应用: 传感器接口集成电路光电二极管
文件页数/大小: 57 页 / 1704 K
品牌: ZMD [ Zentrum Mikroelektronik Dresden AG ]
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ZENTRUM MIKROELEKTRONIK DRESDEN AG  
“ASI for you” IC  
Datasheet  
3.6.4 Master-, Repeater-, Monitor Mode  
In Master-, Repeater- and Monitor Mode the Parameter Port is differently configured than in Slave Mode. The  
pins serve as output channels for additional support signals or become set to high impedance state. There is no  
input function associated with the Parameter Port pins.  
Following support signals are provided at the Parameter Port in Master-, Repeater- and Monitor-Mode.  
Table 17: Parameter Port output signals in Master-, Repeater-, Monitor-Mode  
Pin  
P0  
P1  
P2  
P3  
Master Mode  
Repeater Mode  
Monitor Mode  
Receive Clock  
Power Fail  
Hi-Z  
Hi-Z  
Hi-Z  
Hi-Z  
Receive Clock  
Power Fail  
Receive Strobe – Slave Telegram  
Hi-Z  
Receive Strobe – Slave Telegram  
Receive Strobe – Master Telegram  
Receive Clock is provided to simplify external processing of Manchester-II-coded output data at LED1 pin. The  
availability of a new AS-i telegram bit at LED1 is signaled by a rising edge of receive clock so that the received  
data can simply be clocked into a shift register. The output signal is active high.  
Power Fail signals a breakdown of the AS-i supply voltage. The output signal is active high. Further information  
regarding the Power Fail function refer to chapter 3.8 Fault Indication Input Pin FID.  
Receive Strobe – Slave Telegram is generated after every correctly received AS-i slave telegram. The output  
signal is active high.  
Receive Strobe – Master Telegram is generated after every correctly received AS-i master telegram. The output  
signal is active high.  
The generated pulse width is 1.0µs for both Receive Strobe signals at the output drivers (Hi-Z time). The result-  
ing signal pulse width depends on the external pull-up resistor and the load circuit.  
Copyright © 2006, ZMD AG, Rev.1.4  
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The  
Information furnished in this publication is preliminary and subject to changes without notice.  
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