Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA BYTE COUNT REGISTER CHANNEL 0
(BCRO: I/O Address = 26H to 27H) specifies the number of bytes to be transferred. This register contains 16 bits and may
specify up to 64 KB transfers. When one byte is transferred, the register is decremented by one. If “n” bytes should be
transferred, “n” must be stored before the DMA operation.
Note: All DMA Count Register channels are undefined during reset.
DMA Byte Count Register Channel 0L
DMA Byte Count Register Channel 1L
Mnemonic BCR0L
Mnemonic BCR1L
Address 26
Address 2E
Figure 61. DMA Byte Count Register 0L
Figure 63. DMA Byte Count Register 1L
DMA Byte Count Register Channel 0H
DMA Byte Count Register Channel 0H
Mnemonic BCR0H
Mnemonic BCR1H
Address 27
Address 2F
Figure 62. DMA Byte Count Register 0H
Figure 64. DMA Byte Count Register 0H
1-52
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
