Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
ASCI TIME CONSTANT REGISTERS
If the SS2-0 bits of the CNTLA register are not 111, and the
BRG Mode bit in the ASEXT register is 1, the ASCI divides
the PHI clock by twice (the 16-bit value in these registers,
plus two), to obtain the clock that is presented to the trans-
mitter and receiver for division by 1, 16, or 64 and that can
be output on the CKA1 pin.
ASCI Time Constant Register 0 Low (ASTCOL, I/O Address IAH)
ASCI Time Constant Register 1 Low (ASTCIL), I/O Address ICH)
5
4
3
2
1
0
7
6
Bit
LS 8 Bits of Time Constant
ASCI Time Constant Register 0 High (ASTCOH, I/O Address IBH)
ASCI Time Constant Register 1 High (ASTCIH), I/O Address IDH)
5
4
3
2
1
0
7
6
Bit
MS 8 Bits of Time Constant
Figure 53. ASCI Time Constant Registers
1-48
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
