Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Transmit Enable (bit 4). A CSI/O transmit operation is
started by setting TE to 1. When TE is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the CKS pin. In external clock mode,
the clock is input on the CKS pin. In either case, data is
shifted out on the TXS pin synchronous with the (internal
or external) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears TE to 0, EF is set to 1, and an
interrupt (if enabled by EIE = 1) is generated. TE and RE
are never both set to 1 at the same time. TE is cleared to
0 during RESET and IOSTOP mode.
Timer Data Register Channel 0L
TMDR0L
0CH
7
6
5
4
3
2
1
0
--
--
-- --
-- --
--
--
ASCI Receive Data
SS2, 1, 0: Speed Select 2, 1, 0 (bits 2-0). SS2, SS1 and
SS0 select the CSI/O transmit/receive clock source and
speed. SS2, SS1 and SS0 are all set to 1 during RESET.
Table 10 shows CSI/O Baud Rate Selection.
Figure 42. Timer Register Channel OL
Timer Data Register Channel 0H
Table 7. CSI/O Baud Rate Selection
TMDR0H
SS2 SS1 SS0
Divide Ratio
0D H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷20
÷40
7
6
5
4
3
2
1
0
÷80
÷160
÷320
÷640
÷1280
--
--
-- --
-- --
--
--
Timer Data
Figure 43. Timer Data Register Channel OH
External Clock Input
(less than ÷20.)
After RESET, the CKS pin is configured as an external
clock input (SS2, SS1, SS0 = 1). Changing these values
causes CKS to become an output pin and the selected
clock is output when transmit or receive operations are en-
abled.
CSI/O Transmit/Receive Data Register
(TRDR: I/O Address = 0BH).
7
6
5
4
3
2
1
0
--
--
-- --
-- --
--
--
CSI/O T/R Data
Figure 41. CSI/O Transmit/Receive Data Register 1R
1-44
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
