Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
TDE1, 0: Timer Down Count Enable (bits 1, 0). TDE1
and TDE0 enable and disable down counting for TMDR1
and TMDR0, respectively. When TDEn (n = 0, 1) is set to
1, down counting is stopped and TMDRn is freely read or
written. TDE1 and TDE0 are cleared to 0 during RESET
and TMDRn will not decrement until TDEn is set to 1.
ASCI EXTENSION CONTROL REGISTER CHANNEL 0 (ASEXT0) AND CHANNEL 1 (ASEXT1)
Note: This register controls functions that have been
added to the ASCIs in the Z80180/Z8S180/Z8L180 family.
Note: All bits in this register reset to zero.
ASCI Extension Control Register 0(ASEXT0 I/O Address = 12H)
5
4
3
2
1
0
Bit
Bit
7
6
BRGO
Mode
Break
Nab
Send
Break
Reserved
XI
Break
DCDO
CTSO
ASCI Extension Control Register 1 (ASEXT1 I/O Address = 13H)
5
4
3
2
1
0
7
6
Send
Break
BRGI
Mode
Break
Enab
Reserved
Reserved
Reserved
XI
Break
Figure 47. ASCI Extension Control Registers, Channel 0 and 1
DCD0 dis (bit 6, ASCI0 only). If this bit is 0, then the
DCD0 pin “auto-enables” the ASCI0 receiver, such that
when the pin is negated/High, the Receiver is held in a RE-
SET state. The state of the DCD-pin has no effect on re-
ceiver operation. In either state of this bit, software can
read the state of the DCD0 pin in the STAT0 register, and
the receiver will interrupt on a rising edge of DCD0.
0 bits, to obtain the clock that is presented to the transmit-
ter and receiver and that can be output on the CKA pin. If
SS2-0 are not 111, and this bit is 1, the Baud Rate Gener-
ator divides PHI by twice (the 16-bit value programmed
into the Time Constant Registers, plus two). This mode is
identical to the operation of the baud rate generator in the
ESCC.
CTS0 dis (bit 5, ASCI0 only). If this bit is 0, then the CTS0
pin “auto-enables” the ASCIO transmitter, in that when the
pin is negated/high, the TDRE bit in the STAT0 register is
forced to 0. If this bit is 1, the state of the CTS0 pin has no
effect on the transmitter. Regardless of the state of this bit,
software can read the state of the CTS0 pin the CNTLB0
register.
Break Enable (bit 2). If this bit is 1, the receiver will detect
Break conditions and report them in bit 1, and the transmit-
ter will send Breaks under the control of bit 0.
Break Detect (bit 1). The receiver sets this read-only bit
to 1 when an all-zero character with a Framing Error be-
comes the oldest character in the Rx FIFO. The bit is
cleared when software writes a 0 to the EFR bit in CNTLA
register, also by Reset, by IOSTOP mode, and for ASCIO
if the DCD0 pin is auto-enabled and is negated (high).
X1 (bit 4). If this bit is 1, the clock from the Baud Rate Gen-
erator or CKA pin is taken as a “1X” bit clock (this is some-
times called “isochronous” mode). In this mode, receive
data on the RXA pin must be synchronized to the clock on
the CKA pin, regardless of whether CKA is an input or an
output. If this bit is 0, the clock from the Baud Rate Gener-
ator or CKA pin is divided by 16 or 64 per the DR bit in
CNTLB register, to obtain the actual bit rate. In this mode,
receive data on the RxA pin need not be synchronized to
a clock.
Send Break (bit 0). If this bit and bit 2 are both 1, the trans-
mitter holds the TXA pin low to send a Bread condition.
The duration of the Bread is under software control (one of
the PRTs or CTCs can be used to time it). This bit resets
to 0, in which state TXA carries the serial output of the
transmitter.
BRG Mode (bit 3). If the SS2-0 bits in the CNTLB register
are not 111, and this bit is 0, this ASCI's Baud Rate Gen-
erator divides PHI by 10 or 30, depending on the DR bit in
CNTLB, and then by a power of two selected by the SS2-
1-46
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
