Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
DMA DESTINATION ADDRESS REGISTER CHANNEL 0
(DAR0: I/O Address = 23H to 25H) specifies the physical destination address for channel 0 transfers. The register con-
tains 20 bits and can specify up to 1024 KB memory addresses or up to 64 KB I/O addresses. Channel 0 destination can
be memory, I/O, or memory mapped I/O. For I/O, the MS bits of this register identify the Request Handshake signal for
channel 0.
1
DMA Destination Address Register Channel
0L
DMA Destination Address Register Channel
0B
Mnemonic DAR0L
Mnemonic DAR0B
Address 23
Address 25
Figure 58. DMA Destination Address Register
Channel 0L
Figure 60. DMA Destination Address Register
Channel 0B
Note: In the R1 and Z Mask, these DMA registers are
expanded from 4 bit to 3 bits in the package version of CP-
68
DMA Destination Address Register Channel
0H
Mnemonic DAR0H
A19*
A18
A17
A16
DMA Transfer
Request
Address 24
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
DREQ0
TDR0 (ASCI0)
TDR1 (ASCI1)
Not Used
Figure 59. DMA Destination Address Register
Channel 0H
DS971800401
P R E L I M I N A R Y
1-51
ZILOG [ ZILOG, INC. ]
