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ꢂꢀ*ꢎꢄꢂꢏ*ꢍꢆꢄTheASCIReceiveDataRegisterisaread-only
register. When a complete incoming data byte is assembled
in 454, it is automatically transferred to the 4 character Re-
ceive Data First-In First-Out ((+(1) memory. The oldest
character in the (+(1 (if any) can be read from the Receive
Data Register (4&4). The next incoming data byte can be
shifted into 454 while the (+(1 is full. Thus, the ASCI re-
ceiver is well buffered.
Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation is not affected
by this 4'#& operation.
#5%+ꢄ4GEGKXGꢄ5JKHVꢄ4GIKUVGTꢄꢂꢎꢁꢄꢌ454ꢂꢎꢁꢍꢆꢄThis register
receives data shifted in on the 4:# pin. When full, data is
automatically transferred to the ASCI Receive Data Regis-
ter (4&4) if it is empty. If 454 is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
#5%+ꢄ56#675ꢄ(+(1
This four-entry (+(1 contains Parity Error, Framing Error,
acter in the receive data (+(1. The status of the oldest char-
RxOverrun, andBreakstatusbitsassociatedwitheachchar-
acter (if any) can be read from the ASCI status registers.
#5%+ꢄ%*#00'.ꢄ%10641.ꢄ4')+56'4ꢄ#
#5%+ꢅ%QPVTQNꢅ4GIKUVGTꢅ#ꢅꢀꢅꢈ%06.#ꢀꢓꢅ+ꢌ1ꢅ#FFTGUUꢅꢐꢅꢀꢀ*ꢉ
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4ꢌ9
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(KIWTG ꢋꢋꢆ #5%+ꢄ%JCPPGNꢄ%QPVTQNꢄ4GIKUVGTꢄ#
/2'ꢅꢄ/WNVKꢊ2TQEGUUQTꢄ/QFGꢄ'PCDNGꢄꢌ$KVꢄꢐꢍꢆꢄThe ASCI
featuresamultiprocessorcommunicationmodethatutilizes
an extra data bit for selective communication when a num-
ber of processors share a common serial bus. Multiproces-
sor data format is selected when the /2 bit in %06.$ is set
to 1. If multiprocessor mode is not selected (/2 bit in
%06.$ꢅꢐꢅꢀ), /2' has no effect. If multiprocessor mode
is selected, /2' enables or disables the wake-up feature as
follows. If /$' is set to 1, only received bytes in which the
multiprocessorbitꢅ(/2$ )ꢅꢐꢅꢄ canaffectthe4&4(anderror
flags. Effectively, other bytes (with /2$ꢅꢐꢅꢀ) are ignored
by the ASCI. If /2' is reset toꢅ0, all bytes, regardless of
the state of the/2$ data bit, affect the4'&4 and errorflags.
/2' is cleared toꢅ0during 4'5'6.
4'ꢅꢄ4GEGKXGTꢄ'PCDNGꢄꢌ$KVꢄꢈꢍꢆꢄWhen4' is set to1, theASCI
transmitter is enabled. When 6' is reset toꢅ0, the transmitter
is disables and any transmit operation in progress is inter-
rupted. However, the 6&4'flagisnotresetandthe previous
contents of 6&4' are held. 6' is cleared toꢅ0in +15612
mode during 4'5'6.
6'ꢅꢄ6TCPUOKVVGTꢄ'PCDNGꢄꢌ$KVꢄꢑꢍꢆꢄWhen 6' is set to 1, the
ASCI receiver is enabled. When 6' is reset toꢅ0, the trans-
mitter is disabled and any transmit operation in progress is
interrupted. However, the6&4' flagisnot reset andthe pre-
&5ꢀꢀꢁꢀꢀꢂꢃ</2ꢀꢂꢀꢀ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
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