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#
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WhiletheZ8S180/Z8L180isin+&.' mode, it grants the bus
to an external Master if the BREXT bit (CCR5) is 1. Figure
16 depicts the timing for this sequence.
After the external Master negates the Bus Request, the
Z8S180/Z8L180 disables the2*+ clock andremainsin +&.'
mode.
0QVGꢅ A response to a bus request takes 8 clock cycles longer
than in normal operation.
ꢂꢂ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
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ZILOG [ ZILOG, INC. ]
