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ZiLOG
ing the bus to an external Master during 56#0&$; mode,
when the $4':6 bit in the CPU Control Register (%%4ꢏ)
is 1.
a &+ instruction, the processor restarts by executing the in-
struction(s) following the 5.2 instruction. If +06ꢀ, or +06ꢄ
or +06ꢂ goes inactive before the end of the clock stabiliza-
tion delay, the Z8S180/Z8L180 stays in 56#0&$; mode.
As described previously for 5.''2 and +&.' modes, when
the MPU leaves 56#0&$; mode due to 0/+ Low or an en-
abled +06ꢀ–+06ꢂ Low when the +'(, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
5.2 instruction. If the Z8S180/Z8L180 leaves 56#0&$;
mode due to an external interrupt request that's enabled in
the +06ꢌ64#2 Control Register, but the +'(, bit isꢅ0due to
Figure 17 indicates the timing for leaving 56#0&$; mode
due to an interrupt request.
17
0QVGꢅ The Z8S180/Z8L180 takes either 64 or 2 (131,072)
clocks to restart, depending on the CCR3 bit.
1REQFGꢅ(GVEJꢅQTꢅ+PVGTTWRV
#EMPQYNGFIGꢅ%[ENG
56#0&$;ꢅ/QFG
6
6
6
6
2*+
ꢂ
ꢃꢅQTꢅꢁꢎꢃ%[ENGꢅ&GNC[ꢅHTQOꢅ+06Kꢅ#UUGTVGF
0/+
QT
+06ꢀꢇꢅ+06ꢄꢇꢅ+06ꢂ
#
#
(((((*
*#.6
/ꢄ
(KIWTG ꢁꢐꢆ <ꢀ5ꢁꢀꢂꢃ<ꢀ.ꢁꢀꢂꢄ56#0&$;ꢄ/QFGꢄ'ZKVꢄ&WGꢄVQꢄ'ZVGTPCNꢄ+PVGTTWRV
While the Z8S180/Z8L180 is in 56#0&$; mode, it grants
the bus to an external Master if the $4':6 bit (%%4ꢏ) is 1.
Figure 18 indicates the timing of this sequence. The device
pending on the CCR3 bit. The latter (not the 37+%-ꢅ4'ꢃ
%18'4;)casemaybeprohibitive formanydemand-driven
external Masters. If so, 37+%-ꢅ4'%18'4; or +&.' mode
can be used.
17
takes 64 or 2 (131,072) clock cycles to grant the bus de-
ꢂꢎ
2ꢅ4ꢅ'ꢅ.ꢅ+ꢅ/ꢅ+ꢅ0ꢅ#ꢅ4ꢅ;
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ZILOG [ ZILOG, INC. ]
