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The Z8S180/Z8L180 leaves *#.6 mode in response to:
Low on 4'5'6
In case of an interrupt, the return address is the instruction
following the *#.6 instruction. The program can either
branch back to the *#.6 instruction to wait for another in-
terrupt or can examine the new state of the system/applica-
tion and respond appropriately.
Interrupt from an enabled on-chip source
External request on 0/+
Enabled external request on +06ꢀ, +06ꢄ, or +06ꢂ
Interrupt
HALT Opcode Fetch Cycle
HALT Mode
Acknowledge Cycle
T2
T3
T1 T2
PHI
INTi, NMI
A19–A0
HALT
M1
HALT Opcode Address + 1
HALT Opcode Address
MREQ
RD
Note:
indicates an indefinite delay.
(KIWTG ꢁꢋꢆ *#.6ꢄ6KOKPI
5.''2ꢄ/QFGꢆꢄThismodeisenteredbykeepingthe+15612
bit (ICR5) and bits 3 and 6 of the CPU Control Register
(CCR3, CCR6) all zero and executing the 5.2 instruction.
The oscillator and 2*+ output continue operating, but are
blocked from the CPU core and DMA channels to reduce
power consumption. DRAM refresh stops, but interrupts
and granting to an external Master can occur. Except when
the bus is granted to an external Master, A19–0 and all con-
trol signals except *#.6 are maintained High. *#.6 is
Low. I/O operations continue as before the 5.2 instruction,
except for the DMA channels.
an external request on 0/+, or an external request on +06ꢀ,
+06ꢄ, or +06ꢂ.
Ifaninterruptsourceisindividuallydisabled,itcannotbring
the Z8S180/Z8L180 out of 5.''2 mode. If an interrupt
source is individually enabled, and the +'( bit is 1 so that
interrupts are globally enabled (by an EI instruction), the
highest priority active interrupt occurs with the return ad-
dress being the instruction after the 5.2 instruction. If an
interrupt source is individually enabled, but the +'( bit isꢅ0
so that interrupts are globally disabled (by a DI instruction),
the Z8S180/Z8L180 leaves 5.''2 mode by simply execut-
ing the following instruction(s).
The Z8S180/Z8L180 leaves 5.''2 mode in response to a
Lowon4'5'6, aninterruptrequestfromanon-chipsource,
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ZILOG [ ZILOG, INC. ]
