Z8FMC16100 Series Flash MCU
Product Specification
297
Op Code Maps
Figure 57 and Table 166 provide descriptions of the Op Code map data and the abbrevia-
tions. Figures 58 and 59 provide information about each of the eZ8 CPU instructions.
Op Code
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
Op Code
Upper Nibble
A
CP
R2,R1
First Operand
After Assembly
Second Operand
After Assembly
Figure 57. Op Code Map Cell Description
Table 166. Op Code Map Abbreviations
Abbreviation
b
cc
X
Description
Bit position
Condition code
8-bit signed index or
displacement
Abbreviation
IRR
p
r
Description
Indirect Register Pair
Polarity (0 or 1)
4-bit Working Register
DA
ER
Destination address
Extended Addressing register r1, R1, Ir1, Irr1, IR1,
rr1, RR1, IRR1, ER1
R
8-bit register
Destination address
IM
Immediate data value
r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2
Source address
Ir
IR
Irr
Indirect Working Register
Indirect register
Indirect Working Register Pair RR
RA
rr
Relative
Working Register Pair
Register Pair
PS024604-1005
P R E L I M I N A R Y
Op Code Maps
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