Z8FMC16100 Series Flash MCU
Product Specification
83
Bit
Value
(H)
Description
Position
[7:6]
Must be 0.
Reserved
[5]
Debug Entry Fault Mask
DBGMSK
0
1
Entering CPU DEBUG Mode generates a PWM fault.
Entering CPU DEBUG mode does not generate a PWM fault.
[4:3]
Must be 0.
Reserved
[2]
Fault 1 Fault Mask
F1MASK
0
1
Fault 1 generates a PWM fault.
Fault 1 does not generate a PWM fault.
[1]
Comparator Fault Mask
C0MASK
0
1
Comparator generates a PWM fault.
Comparator does not generate a PWM fault.
[0]
Fault Pin Mask
F0MASK
0
1
Fault0 pin generates a PWM fault.
Fault0 pin does not generate a PWM fault.
Note: This register can only be written when PWENis cleared.
PWM Fault Status Register
The PWM Fault Status (PWMFSTA) Register, shown in Table 53, provides status of fault
inputs and timer reload.. The fault flags indicate which fault source is active. If a fault
source is masked the flag in this register will not be set if the source is asserted. The
reload flag is set when the timer compare vaules are updated. Clear flags by writing a 1 to
the flag bits. Fault flag bits can only be cleared if the associated fault source has deas-
serted.
PS024604-1005
P R E L I M I N A R Y
PWM Fault Status Register
ZILOG [ ZILOG, INC. ]
