Z8 Encore!® Motor Control Flash MCUs
Product Specification
80
PWM Control 1 Register
The PWM Control 1 (PWMCTL1) Register, shown in Table 49, controls portions of PWM
operation.
Table 49. PWM Control 1 Register (PWMCTL1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
Pol23
0
2
Pol10
0
1
0
RLFREQ[1:0]
INDEN
Pol45
PRES[1:0]
00
00
0
0
R/W
R/W
R/W
R/W
R/W
R/W
F21H
ADDR
Bit
Value
(H)
Description
Reload Event Frequency
Position
[7:6]
RLFREQ[1:0]
This bit field is buffered. Changes to the reload event frequency takes effect at
the end of the current PWM period. Reads always return the bit values from the
temporary holding register.
00
01
10
11
PWM reload event occurs at the end of every PWM period.
PWM reload event occurs once every 2 PWM periods.
PWM reload event occurs once every 4 PWM periods.
PWM reload event occurs once every 8 PWM periods.
[5]
Independent PWM Mode Enable
INDEN
0
This bit may only be altered when PWEN(PWMCTL0) cleared.
PWM outputs operate as 3 complementary pairs.
1
1
0
1
0
1
0
PWM outputs operate as 6 independent channels.
Invert Ouput polarity for channel pair PWM2.
Non-inverted polarity for channel pair PWM2.
Invert Ouput polarity for channel pair PWM1.
Non-inverted polarity for channel pair PWM1.
Invert Ouput polarity for channel pair PWM0.
Non-inverted polarity for channel pair PWM0.
[4]
Pol2
[3]
Pol1
[2]
Pol0
Pulse-Width Modulator
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
