Z8FMC16100 Series Flash MCU
Product Specification
87
PWM Output Control Register
The PWM Output Control (PWMOUT) Register, shown in Table 56, enables modulator
control of the six PWM output signals. Output control is enabled by the OUTCTL bit in
the PWMCTL0 register. The Pulse-Width Modulator continues to operate, but has no
effect on the disabled PWM pins. If a fault condition is detected all PWM outputs are
forced to their selected OFF state.
.
Table 56. PWM Output Control Register (PWMOUT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved Reserved
OUT2L
OUT2H
OUT1L
OUT1H
OUT0L
OUT0H
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
F27H
ADDR
Bit
Value
(H)
Description
Position
[7,6]
Must be 0.
Reserved
[5, 3, 1]
OUT2L/
OUT1L/
OUT0L
PWM 2L/1L/0L Output Configuration
PWM 2L/1L/0L output signal is enabled and controlled by PWM.
PWM 2L/1L/0L output signal is in low-side off-state.
0
1
[4, 2, 0]
OUT2H/
OUT1H/
OUT0H
PWM 2H/1H/0H Output Configuration
0
1
PWM 2H/1H/0H output signal is enabled and controlled by PWM.
PWM 2H/1H/0H output signal is in high-side off-state.
Current Sense ADC Trigger Control Register
An ADC trigger is generated when the PWM output signals match the state specified by
the Current-Sense ADC-Trigger control register. The match logic is an AND-OR tree that
will solve to true if based on the register settings. An ADC conversion will be triggered on
the rising edge of this signal. The logic equation for the adc-trigger is:
ADCTRIGGER = CSTPOL ^ (
( HEN & PWM0H &PWM1H & PWM2H) |
( LEN & PWM0L &PWM1L & PWM2L) |
( nHEN & !PWM0H &!PWM1H & !PWM2H) |
( nLEN & !PWM0H & !PWM1H & !PWM2H) )
PS024604-1005
P R E L I M I N A R Y
PWM Output Control Register
ZILOG [ ZILOG, INC. ]
